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M5M54R04AJ-10 - 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM

Description

A0 1 A1 2 application.

A2 3 address inputs A3 4 These devices operate on a single 3.3V supply, and are A 4 5 select directly TTL compatible.

Features

  • data inputs/.
  • Fast access time M5M54R04AJ-10 10ns(max) DQ2 10 outputs M5M54R04AJ-12 12ns(max) write control W 11 input M5M54R04AJ-15 15ns(max) A5 12 A6 13.
  • Single +3.3V power supply address A7 14 inputs.
  • Fully static operation : No clocks, No refresh A8 15.
  • Common data I/O A9 16.
  • Easy memory expansion by S.
  • Three-state outputs : OR-tie capability Outline.
  • OE prevents data contention in the I/O bus.
  • Directly TTL compatible : All i.

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Full PDF Text Transcription

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MITSUBISHI LSIs 1998.11.30 Ver.B PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change M5M54R04AJ-10,-12,-15 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M54R04AJ is a family of 1048576-word by 4-bit static RAMs, fabricated with the high performance CMOS A0 1 A1 2 application. A2 3 address inputs A3 4 These devices operate on a single 3.3V supply, and are A 4 5 select directly TTL compatible. They include a power down chip input S 6 data inputs/ DQ 1 7 feature as well. outputs(3.3V) VCC 8 (0V) GND 9 FEATURES data inputs/ •Fast access time M5M54R04AJ-10 ... 10ns(max) DQ2 10 outputs M5M54R04AJ-12 ... 12ns(max) write control W 11 input M5M54R04AJ-15 ... 15ns(max) A5 12 A6 13 •Single +3.
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