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M5M4V4265CTP-5 - EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

Download the M5M4V4265CTP-5 datasheet PDF. This datasheet also covers the M5M variant, as both devices belong to the same edo (hyper page) mode 4194304-bit (262144-word by 16-bit) dynamic ram family and are provided as variant models within a single manufacturer datasheet.

General Description

This is a family of 262144-word by 16-bit dynamic RAMs with EDO mode fuction, fabricated with the high performance CMOS process, and is ideal for the buffer memory systems of personal computer graphics and HDD where high speed, low power dissipation, and low costs are essential.

Key Features

  • Type name M5M4V4265CXX-5,-5S M5M4V4265CXX-6,-6S M5M4V4265CXX-7,-7S RAS CAS Address access access access time time time (max. ns) (max. ns) (max. ns) Power OE Cycle dissipaaccess time tion time (max. ns) (min. ns) (typ. mW) NC 11 NC 12 W 13 RAS 14 NC 15 A0 16 A1 17 A2 18 A3 19 (3.3V)VCC 20 50 60 70 13 15 20 25 30 35 13 15 20 90 110 130 408 363 333 XX=TP,J Standard 40 pin SOJ, 44 pin TSOP (II) Single 3.3±0.3V supply Low stand-by power dissipation CMOS Input level 1.8mW (Max) CMOS Input level 36.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M5M-4V42.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MITSUBISHI LSIs MITSUBISHI LSIs M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM DESCRIPTION This is a family of 262144-word by 16-bit dynamic RAMs with EDO mode fuction, fabricated with the high performance CMOS process, and is ideal for the buffer memory systems of personal computer graphics and HDD where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. The lower supply (3.