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M5M4257P-20 - 256K-Bit DRAM

Download the M5M4257P-20 datasheet PDF. This datasheet also covers the M5M4257P-12 variant, as both devices belong to the same 256k-bit dram family and are provided as variant models within a single manufacturer datasheet.

Description

This is a family of 262 144-word by 1-bit dynamic RAMs, fabricated with the high performance N-channel silicon gate MOS process, and is ideal for large-capacity memory systems where high speed, low power dissipation, and low costs are essential.

Features

  • Type name Access time (max) (ns) Cycle time (min) (ns) Power dissipation (typ) (mW) M5M4257P-12 120 230 260 M5M4257P -1.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M5M4257P-12-Mitsubishi.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
M5M4256AJ-10 Page Mode 262144-Bit DRAM Mitsubishi Electric Semiconductor
M5M4256AJ-12 Page Mode 262144-Bit DRAM Mitsubishi Electric Semiconductor
M5M4256AJ-15 Page Mode 262144-Bit DRAM Mitsubishi Electric Semiconductor
M5M4256AJ-85 Page Mode 262144-Bit DRAM Mitsubishi Electric Semiconductor
M5M4256AL-10 Page Mode 262144-Bit DRAM Mitsubishi Electric Semiconductor

Other Datasheets by Mitsubishi Electric

Part Number Description
M5M4257P-12 256K-Bit DRAM
M5M4257P-15 256K-Bit DRAM
M5M4257L-12 256K-Bit DRAM
M5M4257L-15 256K-Bit DRAM
M5M4257L-20 256K-Bit DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MITSUBISHI LSls M5M4257P-12, -15, -20 262 144·BIT (262 144·WORD BY I.BIT) DYNAMIC RAM DESCRIPTION This is a family of 262 144-word by 1-bit dynamic RAMs, fabricated with the high performance N-channel silicon gate MOS process, and is ideal for large-capacity memory systems where high speed, low power dissipation, and low costs are essential. The use of double-layer polysi licon process combined with silicide technology and a singletransistor dynamic storage cell provide high circuit density at reduced costs, and the use of dynamic circuitry including sense amplifiers assures low power dissipation. Multiplexed address inputs permit both a reduction in pins to the standard 16-pin package configuration and an increase in system densities.
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