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M2V28S30ATP - 128M Synchronous DRAM

Description

M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized as 4-bank x 2,097,152-word x 16-bit.

All inputs and outputs are referenced to the rising edge of CLK.

Features

  • M2V28S20/30/40ATP ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time Row to Column Delay Access Time from CLK Ref/Active Command Period Operation Current (Max. ) (Single Bank) (Max. ) (Min. ) (Min. ) (Min. ) (Max. ) (CL=3) (Min. ) V28S20 V28S30 V28S40 Icc6 Self Refresh Current -6 7.5ns 45ns 20ns 5.4ns 67.5ns 100mA 110mA 130mA 2mA -7 10ns 50ns 20ns 6ns 70ns 95mA 100mA 120mA 2mA -8 10ns 50ns 20ns 6ns 70ns 95mA 100mA 120mA 2mA Active to Precharge Command Period - Single 3.3V ±0.3V power supply - Max. Clo.

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128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) PRELIMINARY Some of contents are described for general products and are subject to change without notice. DESCRIPTION M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
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