M2V12D30TP - 512M Double Data Rate Synchronous DRAM

Product Overview

Mitsubishi

Datasheet Details

Part number	M2V12D30TP
Manufacturer	Mitsubishi
File Size	754.04 KB
Description	512M Double Data Rate Synchronous DRAM
Datasheet	M2V12D30TP Datasheet
Note	This datasheet PDF includes multiple part numbers: M2V12D30TP, M2V. Please refer to the document for exact specifications by model.
Additional preview pages of the M2V12D30TP datasheet.

Product details

Description

M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit, M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface.

Features

- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge; - data and data mask are referenced to both edges of DQS - 4 bank operations are controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- sequ.

📁 Similar Datasheet

Other Datasheets by Mitsubishi

M2V12D30TP-10 - 512M Double Data Rate Synchronous DRAM
M2V12D30TP-10L - 512M Double Data Rate Synchronous DRAM
M2V12D30TP-75 - 512M Double Data Rate Synchronous DRAM
M2V12D30TP-75L - 512M Double Data Rate Synchronous DRAM
M2V12D20TP - 512M Double Data Rate Synchronous DRAM
M2V12D20TP-10 - 512M Double Data Rate Synchronous DRAM

Published: May 2, 2005 |