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M2S56D30ATP - 256M Double Data Rate Synchronous DRAM

Download the M2S56D30ATP datasheet PDF (M2S included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 256m double data rate synchronous dram.

Description

M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface.

Features

  • - VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge - Data and data mask are referenced to both edges of DQS - 4-bank operations are controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- seque.

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Note: The manufacturer provides a single datasheet file (M2S-56D.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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DDR SDRAM (Rev.1.44) Mar. '02 MITSUBISHI LSIs M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10 256M Double Data Rate Synchronous DRAM Contents are subject to change without notice. DESCRIPTION M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK.Input data is registered on both edges of data strobes, and output data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40ATP achieve very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
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