M2S28D20ATP, M2S 128M Double Data Rate Synchronous DRAM

Mitsubishi

Description

DDR SDRAM (Rev.0.1) Jun,'00 Preliminary MITSUBISHI LSIs M2S28D20/ 30/ 40ATP 128M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are.
M2S28D20ATP is a 4-bank x 8388608-word x 4-bit, M2S28D30ATP is a 4-bank x 4194304-word x 8-bit, M2S28D40ATP is a 4-bank x 2097152-word x 16-bit, doubl.

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M2S28D20ATP Datasheet Preview — This datasheet PDF includes multiple part numbers: M2S28D20ATP, M2S. Please refer to the document for exact specifications by model.

Datasheet Specifications

Part number: M2S28D20ATP, M2S
Manufacturer: Mitsubishi
File Size: 1.19 MB
Datasheet: M2S-28D.pdf
Description: 128M Double Data Rate Synchronous DRAM
Note: This datasheet PDF includes multiple part numbers: M2S28D20ATP, M2S.
Please refer to the document for exact specifications by model.

Features

* - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each po

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M2S 128M Double Data Rate Synchronous DRAM Mitsubishi

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