M2S12D20TP-10L, M2S 512M Double Data Rate Synchronous DRAM

Mitsubishi

Description

DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM DESCRIPT.
M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit, M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 int.

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M2S12D20TP-10L Datasheet Preview — This datasheet PDF includes multiple part numbers: M2S12D20TP-10L, M2S. Please refer to the document for exact specifications by model.

Datasheet Specifications

Part number: M2S12D20TP-10L, M2S
Manufacturer: Mitsubishi
File Size: 754.04 KB
Datasheet: M2S-12D.pdf
Description: 512M Double Data Rate Synchronous DRAM
Note: This datasheet PDF includes multiple part numbers: M2S12D20TP-10L, M2S.
Please refer to the document for exact specifications by model.

Features

* - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge; - data and da

M2S12D20TP-10L Distributors

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M2S 512M Double Data Rate Synchronous DRAM Mitsubishi

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