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AS5SP512K36 - Synchronous SRAM

Features

  •  Synchronous Operation in relation to the input Clock.
  •  2 Stage Registers resulting in Pipeline operation.
  •  On chip address counter (base +3) for Burst operations.
  •  Self-Timed Write Cycles.
  •  On-Chip Address and Control Registers.
  •  Byte Write support.
  •  Global Write support.
  •  On-Chip low power mode [powerdown] via ZZ pin.
  •  Interleaved or Linear Burst support via Mode pin.
  •  Three Chip Enables for ease of depth expansion without Data Contention.

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📁 Similar Datasheet

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Other Datasheets by Micross

Part Number Description
AS5SP512K18 Synchronous SRAM
AS5SP128K36 Synchronous SRAM
AS5SS256K18 256K x 18 SSRAM
AS5SS256K36 256K x 36 SSRAM
AS58C1001 128K x 8 EEPROM

Full PDF Text Transcription

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Plastic Encapsulated Microcircuit 18Mb, 512K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect FEATURES  Synchronous Operation in relation to the input Clock  2 Stage Registers resulting in Pipeline operation  On chip address counter (base +3) for Burst operations  Self-Timed Write Cycles  On-Chip Address and Control Registers  Byte Write support  Global Write support  On-Chip low power mode [powerdown] via ZZ pin  Interleaved or Linear Burst support via Mode pin  Three Chip Enables for ease of depth expansion without Data Contention.  Two Cycle load, Single Cycle Deselect  Asynchronous Output Enable (OE)  Three Pin Burst Control (ADSP, ADSC, ADV)  3.3V Core Power Supply  3.3V/2.
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