MT4C1M16C3 Datasheet (Micron) - 1 MEG x 16 FPM DRAM

MT4C1M16C3, 1 MEG x 16 FPM DRAM

The 1 Meg x 16 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x16 configuration.

The 1 Meg x 16 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#).

These function identically to a single CAS# on other DRAMs in that eith

MT4C1M16C3 Features

* JEDEC- and industry-standard x16 timing, functions, pinouts, and packages

* High-performance, low-power CMOS silicon-gate process

* Single power supply (+3.3V ±0.3V or 5V ±0.5V)

* All inputs, outputs and clocks are TTL-compatible

* Refresh modes: RAS#-ONLY,