MT48LC1M16A1 Datasheet (Micron)

MT48LC1M16A1, SYNCHRONOUS DRAM

The 16Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 16,777,216 bits.

It is internally configured as a dual 512K x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK).

Each of the 512K x 16-bit banks is organized as

MT48LC1M16A1 Features

* PC100 functionality

* Fully synchronous; all signals registered on positive edge of system clock

* Internal pipelined operation; column address can be changed every clock cycle

* Internal banks for hiding row access/precharge 1 Meg x 16 - 512K x 16 x 2 banks archite