TP5322 Datasheet (Microchip) - P-Channel Vertical DMOS FET

TP5322, P-Channel Vertical DMOS FET

The TP5322 low-threshold Enhancement-mode (normally-off) transistor uses a vertical DMOS structure and a well-proven silicon-gate manufacturing process.

This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperatur

TP5322 Features

* 2.4V Maximum Low Threshold

* High Input Impedance

* 110 pF Maximum Low Input Capacitance

* Fast Switching Speeds

* Low On-Resistance

* Free from Secondary Breakdown

* Low Input and Output Leakage Applications

* Logic-Level In