DSP32C-F35, DSP32C Datasheet (Lucent Technologies)

DSP32C-F35, DSP32C, Digital Signal Processor

Contents of the PDR register may fail to be transferred to memory during a DMA write operation when the falling edge of PEN or PWN aligns near the trailing edge of the output clock (CKO).

If an external device overwrites the PDR, the DMA transaction is not completed.

The status of the parallel data

Data Sheet Addendum November 1996 DSP32C Digital Signal Processor Products Affected This advisory is effective for issue 5 of the DSP32C.

Issue 5 devices are identiﬁed by a device code of the form DSP32C-X35 (where X is replaced by R or F).

The design consideration involves external writes to and reads from the parallel data register (PDR) with a system clock greater than 66 MHz.

Problem Resolution PEN, PWN, and PGN may be synchronized with the DSP clock to eliminate this potential alignment p