L9A0212 Datasheet - LSI

L9A0212 Microprocessor

of the major components of the LR4102, as shown in Figure 1. The CPU performs all arithmetic, logical, shift, and address calculations. The CPU supports EJTAG debug and is closely coupled with the FastMDU. The FastMDU calculates all multiply and divide operations for the LR4102, and provides 4/5 cy.

TinyRISC® LR4102 Microprocessor Datasheet The TinyRISC LR4102 Microprocessor is a compact, high performance 32-bit microprocessor implemented in the LSI Logic G11™ technology. The LR4102 is a complete microprocessor solution with caches, an external bus interface with built-in memory controllers, and on-chip debug. The LR4102 is built using the EZ4102 EasyMACRO subsystem, available to customers through the LSI Logic CoreWare® program. The LR4102 provides a 32-bit FBusMACRO to control all off-chi.

L9A0212 Features

* Components

* Caches

* 16 Kbytes of two-way set-associative I-Cache 8 Kbytes of direct-mapped D-Cache

* R3000 MIPS CPU executes MIPS II and MIPS16 instructions 32-bit FBus, a fast demultiplexed multimaster bus, with built in control of:

L9A0212 Datasheet (357.89 KB)