L74VHC1G125 - Noninverting 3-State Buffer

LRC

Datasheet Details

High Speed: tPD = 3.5 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C Power Down Protection Provided on Inputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 58; Equivalent Gates = 15 Pb.
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Published: Jun 20, 2011 |