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ML620Q558 - Ultra Low Power 16-bit Microcontroller

Download the ML620Q558 datasheet PDF (ML620Q536 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for ultra low power 16-bit microcontroller.

Description

This LSI family is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I2C bus interface (master), supply voltage level detect circuit, RC oscillation type A/D converter, and successive approximation type A/D converter are incorp

Features

  • CPU.
  • 16-bit RISC CPU (CPU name: nX-U16/100).
  • Instruction system: 16-bit instructions.
  • Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit operation, bit logic operations, jump, conditional jump, call return stack operation, arithmetic shift, and so on.
  • On-Chip debugs function.
  • Minimum instruction execution time 30.5 µs (@ 32.768 kHz system clock) 62.5 ns (@16 MHz system clock).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ML620Q536-LAPISSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ML620Q558
Manufacturer LAPIS Semiconductor
File Size 614.21 KB
Description Ultra Low Power 16-bit Microcontroller
Datasheet download datasheet ML620Q558 Datasheet
Other Datasheets by LAPIS Semiconductor

Full PDF Text Transcription

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ML620Q53x/54x/Q55x (x:6,8) Ultra Low Power 16-bit Microcontroller PEDL620Q53x_54x_55x-06 Issue Date:July 30,2015 Preliminary GENERAL DESCRIPTION This LSI family is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I2C bus interface (master), supply voltage level detect circuit, RC oscillation type A/D converter, and successive approximation type A/D converter are incorporated around 16-bit CPU nX-U16/100. The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture parallel processing. The rich peripheral circuits such as I/O port, Serial interface and Timers are installed.
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