Description
, page 9)
2
FN9134.1
ISL6534 Block Diagram
VCC VREF VCC12
VCC5 POWER ON RESET AND CONTROL
VCC5 5.8V
30µA
BOOT1
SS1/EN1 VCC5
REFERENCE BIAS CURRENT
3.3V OUTPUT1 DRIVERS
30µA
0.6V
3.3V
GATE CONTROL LOGIC DEAD-TIME CONTROL
UGATE1
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SS2/EN2 VCC5
LGATE1
30µA
SS3/EN3 3.3V CLOCK AND SAWTOOTH GENERATOR BOOT2
PGOOD = all 3 SS ramps done with no COMP short
OUTPUT2 DRIVERS GATE CONTROL LOGIC DEAD-TIME CONTROL UGATE2
LGATE2 PGOOD
FS/SYNC COMP1 3.3V FB1 0.6V 1-2 CLOCK
Features
- Two Synchronous-Rectified Buck Controllers - Voltage Mode control - VIN range up to 12V - VOUT range from 0.6V to 6V - 12V LGATE drivers; up to 12V Boot Strap for UGATE.
- Switcher References - 0.6V Reference for OUT1 (0.8% Accurate) - 3.3V Reference Output for OUT2 (0.8% Accurate) - External Reference Input for OUT2 - Buffered VTT Reference Output.
- Switcher clocking - Phase options for Optimal Clock Relationship - Resistor-Selectable Switching Frequency (300kHz default.
6534CV_IntersilCorporation.pdf
