Description
3 2 Interface Signals 3 2 1 DREQn and EDACK (0
2) 3 2 2 HOLD and HLDA 3 2 3 EOP 3 3 Modes of Operation 3 3 1 Target Requester Definition 3 3 2 Buffer Transfer Processes 3 3 3 Data Transfer Modes 3 3 4 Channel Priority Arbitration 3 3 5 Combining Priority Modes 3 3 6 Bus Operation 3 4 Bus Arbitration and Handshaking 3 4 1 Synchronous and Asynchronous Sampling of DREQn and EOP 3 4 2 Arbitration of Cascaded Master Requests 3 4 3 Arbitration of Refresh Requests PAGE
6 6 7 8 9 10 10 11 11 1
Features
- of the M82380 Each module has a corresponding detailed section later in this data sheet Those sections should be referred to for design and programming information
1 1 M82380 Architecture
The M82380 is comprised of several computer system functions that are normally found in separate LSI and VLSI components These include a highperformance eight-channel 32-bit Direct Memory Access Controller a 20-level Programmable Interrupt Controller which is a superset of the M8259A four 16-bit Programmable I.
M82380_IntelCorporation.pdf
