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IS61NP51218 - 256K x 32/ 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM

Download the IS61NP51218 datasheet PDF (IS6 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 256k x 32/ 256k x 36 and 512k x 18 pipeline no wait state bus sram.

Description

The 8 Meg 'NP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers.

Features

  • 100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single R/W (Read/Write) control pin Clock controlled, registered address, data and control Interleaved or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address p.

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Note: The manufacturer provides a single datasheet file (IS6-1NLP2.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Integrated Silicon Solution Inc

Full PDF Text Transcription

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IS61NP25632 IS61NP25636 IS61NP51218 IS61NLP25632 IS61NLP25636 IS61NLP51218 256K x 32, 256K x 36 and 512K x 18 PIPELINE 'NO WAIT' STATE BUS SRAM ISSI ® PRELIMINARY INFORMATION APRIL 2001 FEATURES • • • • • • • • • • • • • • • • 100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single R/W (Read/Write) control pin Clock controlled, registered address, data and control Interleaved or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining for TQFP Power Down mode Common data inputs and data outputs CKE pin to enable clock and suspend operation JEDEC 100-pin TQFP, 119 PBGA package Single +3.3V power supply (± 5%) NP Version: 3.
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