Description
3.3 VOLT CMOS SuperSync FIFO™ 65,536 x 9 131,072 x 9 .EATURES: * * * * * www.DataSheet4U.com IDT72V281 IDT72.
The IDT72V281/72V291 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls.
Features
* GH in FWFT mode) temporarily and does not disturb the write pointer, programming method, existing timing mode or programma
Applications
* that need to buffer large amounts of data. The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) inpu
