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MK2049-45 - 3.3V Communications Clock PLL

Description

The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation.

The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter.

The second PLL is a translator for frequency multiplication.

Features

  • Packaged in 20 pin SOIC.
  • 3.3 V + 5% operation.
  • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz Locks to 8 kHz + 100 ppm (External mode) Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs Exact internal ratios enable zero ppm error Output rates include T1, E1,.

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Datasheet Details

Part number MK2049-45
Manufacturer Integrated Circuit Systems
File Size 212.72 KB
Description 3.3V Communications Clock PLL
Datasheet download datasheet MK2049-45 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MK2049-45 3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication. Basic configuration is determined by a Mode/Frequency Selection Table. Loop bandwidth and damping factor are programmable via external loop filter component selection. Buffer Mode accepts a 10 to 50MHz input and will provide a jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x ICLK. In this mode the MK2049-45 is ideal for filtering jitter from high frequency clocks.
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