Description
D a t a S h e e t , V 1.0 , N o v .20 0 3 C161S 1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er M i c r o c o n t r o l l er s N e.
and charts stated herein.
Features
* High Performance 16-bit CPU with 4-Stage Pipeline
* 80 ns Instruction Cycle Time at 25 MHz CPU Clock
* 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
* Enhanced Boolean Bit Manipulation Facilities
* Additional Instructions to Support HLL and Operat
Applications
* VDD
VSS
XTAL1 XTAL2 RSTIN RSTOUT NMI EA ALE RD WR/WRL Port 5 2 bit
MCA05504
PORT0 16 bit PORT1 16 bit Port 2 7 bit C161S Port 3 12 bit Port 4 6 bit Port 6 4 bit
Figure 1
Logic Symbol
Data Sheet
3
V1.0, 2003-11
C161S
General Device Information
2.2
Pin Configuration and Definition
P5.15/
