| Part number | IS61QDPB42M18A1, IS61QDPB42M18A |
|---|---|
| Manufacturer | ISSI |
| File Size | 652.96 KB |
| Description | 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM |
| Datasheet |
 IS61QDPB42M18A-ISSI.pdf
|
| Note |
This datasheet PDF includes multiple part numbers: IS61QDPB42M18A1, IS61QDPB42M18A. Please refer to the document for exact specifications by model. |
1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and cont
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