Datasheet Details
| Part number | IS61QDPB41M18A |
|---|---|
| Manufacturer | ISSI |
| File Size | 644.30 KB |
| Description | 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM |
| Datasheet |
 IS61QDPB41M18A-ISSI.pdf
|
| Part number | IS61QDPB41M18A |
|---|---|
| Manufacturer | ISSI |
| File Size | 644.30 KB |
| Description | 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM |
| Datasheet |
IS61QDPB41M18A-ISSI.pdf
|
512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support.
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