Description
The and
are synchronous, high-
performance CMOS static random access memory (SRAM)
devices.These SRAMs have separate I/Os, eliminating the
need for high-speed bus turnaround.The rising edge of K
clock initiates the read/write operation, and all internal
operations are self-timed.Refer to the
for a description of the basic
operations of these
SRAMs.Read and
write addresses are registered on alternating rising edges of
the K clock.Read and write performed in double data rate.The
Features
- 512Kx36 and 1Mx18 configuration available.
- On-chip Delay-Locked Loop (DLL) for wide data valid window.
- Separate independent read and write ports with concurrent read and write operations.
- Synchronous pipeline read with EARLY write operation.
- Double Data Rate (DDR) interface for read and write input ports.
- 2.5 Cycle read latency.
- Fixed 2-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and co.