Datasheet Specifications
- Part number
- ICS548-03
- Manufacturer
- ICST
- File Size
- 85.04 KB
- Datasheet
- ICS548-03_ICST.pdf
- Description
- Low Skew Clock Inverter and Divider
Description
www.DataSheet4U.com ADVANCE INFORMATION ICS548-03 Low Skew Clock Inverter and Divider .
Features
* Packaged in 16 pin narrow (150 mil) SOIC Input clock up to 160 MHz in the non-PLL mode Provides clock outputs of CLK, CLK, and CLK/2 Low skew (500 ps) on CLK, CLK, and CLK/2 All outputs can be tri-stated Entire chip can be powered down by cApplications
* that to need maintain low phase noise in the clock tree, the non-PLL (when S3=S2=1) mode should be used. This chip is not a zero delay buffer. Many applications may be able to use the ICS527 for zero delay dividers. Block Diagram S3:S0 4 Clock Synthesis and Divider Circuitry Output Buffer OutpuICS548-03 Distributors
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