H5DU1262GTR - 128Mb DDR SDRAM

Hynix Semiconductor

Datasheet Details

Part number	H5DU1262GTR
Manufacturer	Hynix Semiconductor
File Size	409.15 KB
Description	128Mb DDR SDRAM
Datasheet	H5DU1262GTR_HynixSemiconductor.pdf

and is subject to change without notice.

VDD, VDDQ = 2.3V min ~ 2.7V max (Typical 2.5V Operation +/- 0.2V for DDR266, 333 ,400 and 500) All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chi.

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Published: Jul 15, 2010 |