Datasheet Details
| Part number | GX28E01-100 |
|---|---|
| Manufacturer | GXCAS |
| File Size | 325.21 KB |
| Description | 1K-Bit Protected 1-Wire EEPROM |
| Datasheet |
 GX28E01-100 Datasheet
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Description
The GX28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1).
The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations.
Features
- 1024 bits of EEPROM memory partitioned into four pages of 256 bits.
- On-chip 512-bit SHA-1 engine to compute 160-bit Message Authentication Codes (MAC) and to generate secrets.
- Write access requires knowledge of the secret and the capability of computing and transmitting a 160-bit MAC as authorization.
- User-programmable page write-protection for page 0, page 3 or all four pages together.
- User-programmable OTP EPROM emulation mode for page 1 ("write to 0").
- Communica.