GX28E01-100 Datasheet (GXCAS) - 1K-Bit Protected 1-Wire EEPROM

GX28E01-100, 1K-Bit Protected 1-Wire EEPROM

The GX28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1).

The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations.

All memory page

GX28E01-100 Features

* 1024 bits of EEPROM memory partitioned into four pages of 256 bits

* On-chip 512-bit SHA-1 engine to compute 160-bit Message Authentication Codes (MAC) and to generate secrets

* Write access requires knowledge of the secret and the capability of computing and transmitting a 160-bit MAC