GS88118 - (GS88118 / GS88136T) Sync Burst SRAMs

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GS88118 (GS88118 / GS88136T) Sync Burst SRAMs by GSI - Datasheet Preview — Datasheet preview – GS88118

Datasheet Details

Part number	GS88118
Manufacturer	GSI
File Size	345.49 KB
Description	(GS88118 / GS88136T) Sync Burst SRAMs
Datasheet	GS88118 Datasheet
Additional preview pages of the GS88118 datasheet.

Product details

Description

Applications The GS88118//36T is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter.Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.Sleep Mode Low power (Sleep mode) is attained through the assertion (high) of the ZZ signal, or by stopping the clock (CK).Memory data is retained

Features

FT pin for user-configurable flow through or pipelined operation.
Single Cycle Deselect (SCD) Operation.
IEEE 1149.1 JTAG-compatible Boundary Scan.
On-chip write parity checking; even or odd selectable.
3.3 V +10%/.
5% core power supply.
2.5 V or 3.3 V I/O supply.
LBO pin for Linear or Interleaved Burst mode.
Internal input resistors on mode pins allow floating mode pins.
Default to Interleaved Pipeline mode.

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Other Datasheets by GSI

GS88118A - (GS88118A - GS88136A) Synchronous Burst SRAMs
GS88118B - (GS88118B - GS88136B) Sync Burst SRAMs
GS88132A - (GS88118A - GS88136A) Synchronous Burst SRAMs
GS88132B - (GS88118B - GS88136B) Sync Burst SRAMs
GS88136A - (GS88118A - GS88136A) Synchronous Burst SRAMs
GS88136B - (GS88118B - GS88136B) Sync Burst SRAMs

Published: Feb 10, 2007 |