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GS8342T18E-333I - 36Mb SigmaCIO DDR-II Burst SRAM

Download the GS8342T18E-333I datasheet PDF (GS8342T08E included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 36mb sigmacio ddr-ii burst sram.

Description

Table Symbol SA NC R/W BW0 BW3 NW0 NW1 LD K K C C TMS TDI TCK TDO VREF ZQ DQ Doff CQ CQ VDD VDDQ VSS Note: NC = Not Connected to die or any other pin Description Synchronous Address Inputs No Connect Synchronous Read/Write Synchronous Byte Writes Nybble Write Control Pin Synchronous

Features

  • Simultaneous Read and Write SigmaCIO™ Interface.
  • Common I/O bus.
  • JEDEC-standard pinout and package.
  • Double Data Rate interface.
  • Byte Write (x36 and x18) and Nybble Write (x8) function.
  • Burst of 2 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation with self-timed Late Write.
  • Fully coherent read and write pipelines.
  • ZQ pin for progra.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8342T08E_GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8342T18E-333I
Manufacturer GSI Technology
File Size 2.33 MB
Description 36Mb SigmaCIO DDR-II Burst SRAM
Datasheet download datasheet GS8342T18E-333I Datasheet

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Full PDF Text Transcription

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Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaCIO™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.
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