Download the GS81302D06GE-500 datasheet PDF.
This datasheet also covers the GS81302D06E-500 variant, as both devices belong to the same 144mb sigmaquad-ii+ burst of 4 sram family and are provided as variant models within a single manufacturer datasheet.
Description
Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input
R
Synchronous Read
Input Active Low
W
Synchronous Write
Input Active Low
BW0
BW3
Synchronous Byte Writes
Input
Active Low x18/x36 only
K
Input Clock
Input Active High
K
Input Clock
Inpu
Features
- 2.5 Clock Latency.
- Simultaneous Read and Write SigmaQuad™ Interface.
- JEDEC-standard pinout and package.
- Dual Double Data Rate interface.
- Byte Write controls sampled at data-in time.
- Burst of 4 Read and Write.
- On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) intputs.
- 1.8 V +100/.
- 100 mV core power supply.
- 1.5 V or 1.8 V HSTL Interface.
- Pipelined read operation.
- Fully c.
GS81302D06GE-500 Datasheet
