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MB90F897S - (MB90895 Series) 16-bit Proprietary Microcontroller

Download the MB90F897S datasheet PDF. This datasheet also covers the MB90895 variant, as both devices belong to the same (mb90895 series) 16-bit proprietary microcontroller family and are provided as variant models within a single manufacturer datasheet.

Description

MB90895 series devices are 16-bit micro general-purpose controllers designed for applications which need highspeed real-time processing.

Features

  • Clock.
  • Built-in PLL clock frequency multiplication circuit.
  • Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 4 times of oscillation clock (for 4-MHz oscillation clock, 4 MHz to 16 MHz).
  • Operation by sub-clock (8.192 kHz) is allowed. (MB90F897).
  • Minimum execution time of instruction: 62.5 ns (when operating with 4-MHz oscillation clock, and 4-time multiplied PLL clock.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MB90895_FujitsuMediaDevices.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Fujitsu Semiconductor Limited

Part Number Description
MB90F897 (MB90895 Series) 16-bit Proprietary Microcontroller
MB90F804 (MB90800 Series) 16-bit Proprietary Microcontroller CMOS
MB90F822 (MB90F822 / MB90F823) 16-bit Proprietary Microcontroller
MB90F822A (MB908xx) 16-bit Proprietary Microcontroller
MB90F823 (MB90F822 / MB90F823) 16-bit Proprietary Microcontroller

Full PDF Text Transcription

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www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS07-13731-1E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90895 Series MB90F897/F897S/MB90V495G s DESCRIPTION MB90895 series devices are 16-bit micro general-purpose controllers designed for applications which need highspeed real-time processing. The devices of this series are high-performance 16-bit CPU micro controllers employing of the dual operation flash memory and CAN controller on LQFP-48 small package. The system, inheriting the architecture of F2MC* family, employs additional instruction ready for high-level languages, expanded addressing mode, enhanced multiply-divide instructions, and enriched bit-processing instructions. Furthermore, employment of 32-bit accumulator achieves processing of long-word data (32 bits).
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