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29F800 - 8M (1M X 8/512K X 16) BIT

Description

The MBM29F800TA/BA is a 8M-bit, 5.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K words of 16 bits each.

The MBM29F800TA/BA is offered in a 48-pin TSOP(I) and 44-pin SOP packages.

This device is designed to be programmed in-system with the standard system 5.0 V VCC supply.

Features

  • Single 5.0 V read, write, and erase Minimizes system level power requirements.
  • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs.
  • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: PFTN.
  • Normal Bend Type, PFTR.
  • Reversed Bend Type) 44-pin SOP (Package suffix: PF).
  • Minimum 100,000 write/erase cycles.
  • High performance 55 ns maximum access time.
  • Sector erase architectu.

📥 Download Datasheet

Datasheet Details

Part number 29F800
Manufacturer Fujitsu Media Devices Limited
File Size 537.49 KB
Description 8M (1M X 8/512K X 16) BIT
Datasheet download datasheet 29F800 Datasheet

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Full PDF Text Transcription

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FUJITSU SEMICONDUCTOR DATA SHEET DS05-20841-4E FLASH MEMORY CMOS 8M (1M × 8/512K × 16) BIT MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90 s FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 44-pin SOP (Package suffix: PF) • Minimum 100,000 write/erase cycles • High performance 55 ns maximum access time • Sector erase architecture One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase.
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