Description
1Mega x 32 SGRAM
EM637327
Table 1. Pin Details of EM637327 Symbol Type Description CLK Input Clock: CLK is driven by the system clock.All SGRAM input signals are sampled on the positive edge of CLK.CLK also increments the internal burst counter and controls the output registers.Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal.If CKE goes low synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended from the next clock
Features
- EM637327
1Mega x 32 SGRAM
Preliminary (08/99)
Pin Assignment (Top View)
DQ29 VSSQ DQ30 DQ31 VSS NC NC NC NC NC NC NC NC NC NC V DD DQ0 DQ1 VSSQ DQ2.
- Fast access time from clock: 4.5/5.5/5.5/6 ns Fast clock rate: 200/166/143/125 MHz Fully synchronous operation Internal pipelined architecture Dual internal banks (512K x 32bit x 2bank) Programmable Mode - CA.