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HB54A2568KN-10B - 256MB DDR SDRAM S.O.DIMM

Description

The HB54A2568KN is Double Data Rate (DDR) SDRAM Module, mounted 256M bits DDR SDRAM (HM5425161BTT) sealed in TSOP package, and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD).

The HB54A2568KN is organized as 16M × 64 × 2 bank mounted 8 pieces of 256M bits DDR SDRAM.

Features

  • 200-pin socket type package (dual lead out)  Outline: 67.6mm (Length) × 31.75mm (Height) × 3.80mm (Thickness)  Lead pitch: 0.6mm.
  • 2.5V power supply (VCC).
  • SSTL-2 interface for all inputs and outputs.
  • Clock frequency: 133 MHz (max) (-A75B/B75B) : 100 MHz (max) (-10B).
  • Data inputs, outputs and DM are synchronized with DQS.
  • 4 banks can operate simultaneously and independently (Component).
  • Burst read/write operation.
  • Programm.

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Datasheet Details

Part number HB54A2568KN-10B
Manufacturer Elpida Memory
File Size 514.63 KB
Description 256MB DDR SDRAM S.O.DIMM
Datasheet download datasheet HB54A2568KN-10B Datasheet

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Other Datasheets by Elpida Memory

Part Number Description
HB54A2568KN-A75B 256MB DDR SDRAM S.O.DIMM
HB54A2568KN-B75B 256MB DDR SDRAM S.O.DIMM
HB54A2568KN 256MB DDR SDRAM S.O.DIMM
HB54A5129F1 512MB Registered DDR SDRAM DIMM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PRELIMINARY DATA SHEET 256MB DDR SDRAM S.O.DIMM HB54A2568KN-A75B/B75B/10B (32M words × 64 bits, 2 Banks) Description The HB54A2568KN is Double Data Rate (DDR) SDRAM Module, mounted 256M bits DDR SDRAM (HM5425161BTT) sealed in TSOP package, and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). The HB54A2568KN is organized as 16M × 64 × 2 bank mounted 8 pieces of 256M bits DDR SDRAM. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.
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