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EDE5108AGBG - 512M bits DDR2 SDRAM

Elpida Memory

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Datasheet Details

Part number	EDE5108AGBG
Manufacturer	Elpida Memory
File Size	674.27 KB
Description	512M bits DDR2 SDRAM
Datasheet	EDE5108AGBG_ElpidaMemory.pdf

EDE5108AGBG Product details

Features

Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

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Published: May 26, 2008 |