DDU8C3-5200 - 5-TAP/ 3.3V CMOS-INTERFACED FIXED DELAY LINE

DDU8C3-5200 Datasheet Preview — Preview of DDU8C3-5200 PDF

Datasheet Details

Part number	DDU8C3-5200
Manufacturer	ETC
File Size	45.78 KB
Description	5-TAP/ 3.3V CMOS-INTERFACED FIXED DELAY LINE
Datasheet	DDU8C3-5200-ETC.pdf

DDU8C3-5200 Product details

Description

PIN DESCRIPTIONS The DDU8C3-series device is a 5-tap digitally buffered delay line.The IN Signal Input signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an T1-T5 Tap Outputs amount determined by the device dash number (See Table).For dash VDD +3.3 Volts numbers 5020 and above, the total delay of the line is measured from IN to GND Ground T5, and the nominal tap-to-tap delay increment is given by one-fifth of the total delay.For dash numbers below 5020, the total del

Features

Five equally spaced outputs Fits standard 8-pin DIP socket Low profile Auto-insertable Input & outputs fully CMOS interfaced & buffered 2 10 T L fan-out capability IN T2 T4 GND data 3 ® delay devices, inc.

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Published: Mar 27, 2005 |