M53D256328A LPDDR SDRAM

ESMT

Description

ESMT LPDDR SDRAM .
Ball Name Function A0~A11, BA0~BA1 Address inputs - Row address A0~A11 - Column address A0~A8 A10/AP : AUTO Precharge BA0~BA1: Bank selects (4 Ban.

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Datasheet Specifications

Part number: M53D256328A
Manufacturer: ESMT
File Size: 2.26 MB
Datasheet: M53D256328A-ESMT.pdf
Description: LPDDR SDRAM

Features

* JEDEC Standard
* Internal pipelined double-data-rate architecture, two data access per clock cycle
* Bi-directional data strobe (DQS)
* No DLL; CLK to DQS is not synchronized.
* Differential clock inputs (CLK and CLK )
* Four bank operation
* CAS Latency : 3
* Burst

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M53D256328A LPDDR SDRAM ESMT

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