M13L32321A - Double Data Rate SDRAM

Product Overview

ESMT

Part number	M13L32321A
Manufacturer	ESMT
File Size	1.13 MB
Description	Double Data Rate SDRAM
Datasheet	M13L32321A Datasheet
Additional preview pages of the M13L32321A datasheet.

z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Two bank operation z CAS Latency : 2, 2.5, 3 z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8 z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) z Data I/O transitions on both edges of data strobe (DQS) z DQS is edge-aligned with data for READs;.

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Published: Sep 20, 2018 |