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M12L128168A-7TVAG2S - 2M x 16 Bit x 4 Banks Synchronous DRAM

Download the M12L128168A-7TVAG2S datasheet PDF. This datasheet also covers the M12L128168A-5TVG2S variant, as both devices belong to the same 2m x 16 bit x 4 banks synchronous dram family and are provided as variant models within a single manufacturer datasheet.

Description

The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst Read single write operation.
  • DQM for masking.
  • Auto & self refresh (self refresh is not supported for VA grade).
  • Refresh - 64 ms refres.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M12L128168A-5TVG2S-ESMT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number M12L128168A-7TVAG2S
Manufacturer ESMT
File Size 1.02 MB
Description 2M x 16 Bit x 4 Banks Synchronous DRAM
Datasheet download datasheet M12L128168A-7TVAG2S Datasheet

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Other Datasheets by ESMT

Part Number Description
M12L128168A-7TVAG2N Synchronous DRAM
M12L128168A-7TVG2N Synchronous DRAM
M12L128168A-7TVG2S 2M x 16 Bit x 4 Banks Synchronous DRAM
M12L128168A-7TG 2M x 16 Bit x 4 Banks Synchronous DRAM
M12L128168A-7TG2N 2M x 16 Bit x 4 Banks Synchronous DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ESMT SDRAM FEATURES  JEDEC standard 3.3V power supply  LVTTL compatible with multiplexed address  Four banks operation  MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave )  All inputs are sampled at the positive going edge of the system clock  Burst Read single write operation  DQM for masking  Auto & self refresh (self refresh is not supported for VA grade)  Refresh - 64 ms refresh period (4K cycle) for V grade -16 ms refresh period (4K cycle) for VA grade M12L128168A (2S) Automotive Grade 2M x 16 Bit x 4 Banks Synchronous DRAM GENERAL DESCRIPTION The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.
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