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M12L128168A-5BVAG2N - Synchronous DRAM

Download the M12L128168A-5BVAG2N datasheet PDF. This datasheet also covers the M12L128168A-5TVG2N variant, as both devices belong to the same synchronous dram family and are provided as variant models within a single manufacturer datasheet.

General Description

The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst Read single write operation.
  • DQM for masking.
  • Auto & self refresh (self refresh is not supported for VA grade).
  • Refresh - 64ms refresh.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M12L128168A-5TVG2N-ESMT.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by ESMT

Part Number Description
M12L128168A-5BVAG2S 2M x 16 Bit x 4 Banks Synchronous DRAM
M12L128168A-5BVG2N Synchronous DRAM
M12L128168A-5BVG2S 2M x 16 Bit x 4 Banks Synchronous DRAM
M12L128168A-5BG 2M x 16 Bit x 4 Banks Synchronous DRAM
M12L128168A-5BG2N 2M x 16 Bit x 4 Banks Synchronous DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ESMT SDRAM FEATURES  JEDEC standard 3.3V power supply  LVTTL compatible with multiplexed address  Four banks operation  MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave )  All inputs are sampled at the positive going edge of the system clock  Burst Read single write operation  DQM for masking  Auto & self refresh (self refresh is not supported for VA grade)  Refresh - 64ms refresh period (4K cycle) for V grade - 16ms refresh period (4K cycle) for VA grade M12L128168A (2N) Automotive Grade 2M x 16 Bit x 4 Banks Synchronous DRAM GENERAL DESCRIPTION The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.