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74LVC2G125 - DUAL BUFFER GATE

Description

The 74LVC2G125 is a dual buffer gate with 3-state outputs.

The device is designed for operation over a power supply range of 1.65V to 5.5V.

The device is fully specified for partial power down applications using IOFF.

Features

  • Wide Supply Voltage Range from 1.65 to 5.5V.
  • ± 24mA Output Drive at 3.3V.
  • CMOS Low Power Consumption.
  • IOFF Supports Partial-Power-Down Mode Operation.
  • Inputs accept up to 5.5V.
  • Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise and fall times. The hysteresis is typically 100mV at VCC = 3.0V.
  • ESD Protection Exceeds JESD 22.
  • 2000-V Human Body Model (A114).
  • Exceeds 1000-V Charged Device Model (C101).
  • Totally Lead.

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Description The 74LVC2G125 is a dual buffer gate with 3-state outputs. The device is designed for operation over a power supply range of 1.65V to 5.5V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing damaging current backflow when the device is powered down. 74LVC2G125 DUAL BUFFER GATE WITH 3-STATE OUTPUTS Pin Assignments (Top View) 1OE 1 8 VCC 1A 2 7 2OE 2Y 3 6 1Y Features  Wide Supply Voltage Range from 1.65 to 5.5V  ± 24mA Output Drive at 3.3V  CMOS Low Power Consumption  IOFF Supports Partial-Power-Down Mode Operation  Inputs accept up to 5.5V  Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise and fall times. The hysteresis is typically 100mV at VCC = 3.0V.