Description
SHM 35-Series is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an ARM® Cortex®-M0 CPU.
Features
- 32-bit MCU Subsystem.
- 48 MHz ARM Cortex-M0 CPU with single-cycle multiply.
- Up to 256 kB of flash with Read Accelerator.
- Up to 32 kB of SRAM.
- DMA engine with 32 channels
Programmable Analog.
- Four opamps that operate in Deep Sleep mode at very low
current levels.
- All opamps have reconfigurable high current pin-drive,
high-bandwidth internal drive, ADC input buffering, and Comparator modes with flexible connectivity allowing input connections to any pin.
- Four curr.
SHM35920-L-Cypress.pdf
