Description
S27KL0642/S27KS0642 3.0 V/1.8 V, 64 Mb (8 MB), HyperRAM Self-Refresh DRAM S27KL0642/S27KS0642, 3.0 V/1.8 V, 64 Mb (8 MB), HyperRAM Self-Refresh DRAM .
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HyperBus Interface 4 Product Overview 6
HyperBus Interface 6 Signal Description 7
Input/Output Summary 7 HyperBus Transaction Details 8
Comma.
Features
* Interface
* HyperBus Interface
* 1.8 V / 3.0 V interface support
* Single-ended clock (CK) - 11 bus signals
* Optional differential clock (CK, CK#) - 12 bus signals
* Chip Select (CS#)
* 8-bit data bus (DQ[7:0])
* Hardware reset (RESET#)
* Bidirectional Read-Write Dat
