Description
10 4.1 CMD Bus and DQ Bus 10 4.2 Database Entry (Data Array and Mask Array) 10 4.3 Arbitration Logic 10 4.4 Pipeline and SRAM Control 11 4.5 Full Logic 11 5.0 SIGNAL DESCRIPTIONS 11 6.0 CLOCKS 13 7.0 REGISTERS 13 7.1 Comparand Registers 13 7.2 Mask Registers 14 7.3 Search Successful Registers (SSR[0:7]) 14 7.4 Command Register 14 7.5 Information Register 15 7.6 Read Burst Address Register 16 7.7 Write Burst Address Register Description 16 7.8 NFA Register 16 8.0 NSE ARCHITECTURE
Features
CYNSE70064A_CypressSemiconductor.pdf
