CY7C2163KV18 - 18-Mbit QDR II+ SRAM Four-Word Burst Architecture

Cypress Semiconductor

Datasheet Details

Part number	CY7C2163KV18
Manufacturer	Cypress Semiconductor
File Size	623.35 KB
Description	18-Mbit QDR II+ SRAM Four-Word Burst Architecture
Datasheet	CY7C2163KV18-CypressSemiconductor.pdf

Separate independent read and write data ports.
Supports concurrent transactions.
550-MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed.

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Published: Mar 14, 2017 |