Datasheet Details
| Part number | CY7C1412V18 |
|---|---|
| Manufacturer | Cypress (Infineon) |
| File Size | 459.26 KB |
| Description | SRAM 2-Word Burst Architecture |
| Datasheet |
 CY7C1412V18 Datasheet
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General Description
The CY7C1410V18, CY7C1425V18, CY7C1412V18, and CY7C1414V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.
QDR-II architecture consists of two separate ports to access the memory array.
Key Features
- Separate Independent Read and Write data ports.
- Supports concurrent transactions.
- 200-MHz clock for high bandwidth.
- 2-Word Burst on all accesses.
- Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 400 MHz) @ 200 MHz www. DataSheet4U. com.
- Two input clocks (K and K) for precise DDR timing.
- SRAM uses rising edges only.
- Two output clocks (C and C) accounts for clock skew and flight time mismatchi.