CY2XP304 - High-Frequency Programmable PECL Clock Generation Module

Cypress Semiconductor

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Datasheet Details

Part number	CY2XP304
Manufacturer	Cypress Semiconductor
File Size	266.93 KB
Description	High-Frequency Programmable PECL Clock Generation Module
Datasheet	CY2XP304_CypressSemiconductor.pdf

CY2XP304 Product details

Description

3.3V Power Supply for Crystal Driver SER_CLK Serial Interface Clock SER_DATA Serial Interface Data PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table CLK_SEL INA,INAB NC Clock Select Input, Internal Pull down.HIGH select INA/INAB, Internal PLL is bypassed.LOW select internal PLL Differential Clock Input pair, used in PLL-bypassed mode No Connect Frequency Table PLL_Mult 0 1 M (PLL Multiplier) x16 x8 Example Input Crystal Frequency 25 MHz 31.25 MHz 15.625 MHz

Features

Period jitter peak-peak 125MHz(max. ) = 55 ps.
Four low-skew LVPECL outputs.
Phase-locked loop (PLL) multiplier select.
Serially-configurable multiply ratios.
Eight-bit feedback counter and six-bit reference counter for high accuracy.
HSTL inputs.
HSTL-to-LVPECL level translation.
125- to 500-MHz output range for high-speed.

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Other Datasheets by Cypress Semiconductor

CY2XP306 - High-frequency Programmable PECL Clock Generation Module
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Published: Jul 30, 2011 |