CS2300-CP Datasheet (Cirrus Logic) - Fractional-N Clock Multiplier

CS2300-CP, Fractional-N Clock Multiplier

The CS2300-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop.

The CS2300-CP is based on a hybrid analog-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL.

This architecture a

CS2300-CP Features

*  Clock Multiplier / Jitter Reduction

* Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source  Internal LC Oscillator for Timing Reference  Highly Accurate PLL Multiplication Factor

* Maximum Error less than 1 PPM in HighResolution Mode