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PDC2 - 32 bit Embedded ASIC Core Peripheral

Description

The Peripheral Data Controller 2 (PDC2) transfers data between on-chip peripherals such as the UART, USART, SSC and SPI and the on- and off-chip memories.

Features

  • Compatible with an Embedded ARM7TDMI™ Processor Generates Transfers to/from Serial Peripherals Such as UART, USART, SSC and SPI Supports Up to 12 Peripherals.
  • Parameterizable on Request One ARM® Cycle Needed for a Transfer from Memory to Peripheral Two ARM Cycles Needed for a Transfer from Peripheral to Memory Fully Scan Testable up to 98% Fault Coverage Can be Directly Connected to the Atmel Implementation.

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    Features • • • • • • • • Compatible with an Embedded ARM7TDMI™ Processor Generates Transfers to/from Serial Peripherals Such as UART, USART, SSC and SPI Supports Up to 12 Peripherals – Parameterizable on Request One ARM® Cycle Needed for a Transfer from Memory to Peripheral Two ARM Cycles Needed for a Transfer from Peripheral to Memory Fully Scan Testable up to 98% Fault Coverage Can be Directly Connected to the Atmel Implementation of the AMBA™ Bridge Not Fully Compatible with AMBA: Retract Response not Supported Description The Peripheral Data Controller 2 (PDC2) transfers data between on-chip peripherals such as the UART, USART, SSC and SPI and the on- and off-chip memories.
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